As shown in FIG. 14, a semiconductor logic circuit is shipped after going through three phases: design, manufacturing, and test. In the test phase, test vectors in each of which a logic value 0 or 1 is assigned to each logic bit are applied to a manufactured semiconductor logic circuit, a test response from the semiconductor logic circuit is observed, the test response is compared with an expected test response, and a determination as to whether the manufactured semiconductor logic circuit is a non-defective product or a defective product. A non-defective product rate is called “yield” and the yield has a great impact on quality, reliability, and manufacturing cost of semiconductor logic circuits.
Generally, a semiconductor logic circuit is a sequential circuit in most cases. The sequential circuit is configured to include a combinational circuit portion constituted by logic elements such as an AND gate, a NAND gate, an OR gate and a NOR gate, and flip-flops each storing a circuit internal state. In this case, the combinational circuit portion includes primary input lines (PIs), pseudo primary input lines (PPIs), primary output lines (POs), and pseudo primary output lines (PPOs) that are flip-flop input lines. Inputs to the combinational circuit portion include those directly applied from the primary input lines and those applied via the pseudo primary input lines. Further, outputs from the combinational circuit portion include those directly appearing on the primary output lines and those appearing on the pseudo primary output lines.
To test the combinational circuit portion of the sequential circuit, it is necessary to apply required test vectors from the primary input lines and the pseudo primary input lines of the combinational circuit portion to the combinational circuit portion, and to observe a test response from the primary output lines and the pseudo primary output lines of the combinational circuit portion. One test vector is configured to include bits corresponding to primary input lines and pseudo primary input lines, respectively. One test response is configured to include bits corresponding to primary output lines and pseudo primary output lines, respectively.
However, output lines (pseudo primary input lines) and input lines (pseudo primary output lines) of the flip-flops of the sequential circuit are usually inaccessible from outside. Due to this, to test the combinational circuit portion has problems of controllability over the pseudo primary input lines and observability of the pseudo primary output lines.
Scan design is known as a main method of solving the problems of the controllability and the observability confronted by testing of the sequential circuit. The full-scan design means replacing flip-flops by scan flip-flops and generating one or a plurality of scan chains using the scan flip-flops. Operations performed by the scan flip-flops are controlled by a scan enable (SE) signal line. For example, if SE=0, each of the scan flip-flops operates similarly to the conventional flip-flops. If a clock pulse is applied, an output value from each of the scan flip-flops is updated to a value from the combinational circuit portion. Further, if SE=1, one scan flip-flop and another scan flip-flop in the same scan chain form one shift register. If a clock pulse is applied, a new value is loaded to the scan flip-flop through shift-in from the outside and, at the same time, a value currently present in the scan flip-flop is loaded to the outside through shift-out. Normally, the scan flip-flops belonging to the same scan chain share the same scan enable (SE) signal line. The scan flip-flops belonging to different scan chains either share the same scan enable (SE) signal line or use different scan enable (SE) signal lines.
A test is conducted on the combinational circuit portion of a full-scan sequential circuit by repeating scan shift and scan capture. The scan shift is performed in a shift mode in which a scan enable (SE) signal is set to a logic value 1. In the shift mode, one or a plurality of clock pulses is applied and one or a plurality of new values is loaded into the scan flip-flops in each scan chain through shift-in from the outside. At the same time, one or a plurality of values currently present in the scan flip-flops in the scan chain is loaded to the outside through shift-out. The scan capture is performed in a capture mode in which the scan enable (SE) signal is set to a logic value 0. In the capture mode, one clock pulse is applied simultaneously to all the scan flip-flops in one scan chain, and values of the pseudo primary output lines of the combinational circuit portion are loaded into all the scan flip-flops.
The scan shift is used to apply test vectors to the combinational circuit portion via the pseudo primary input lines and to observe a test response from the combinational circuit portion via the pseudo primary output lines. The scan capture is used to load the test response from the combinational test portion into the scan flip-flops. By repeating the scan shift and the scan capture for all the test vectors, the combinational circuit portion can be tested. A test method of this type is called “scan testing”.
In the scan testing, application of test vectors to the combinational circuit portion includes direct application of test vectors from the primary inputs and application thereof by means of the scan shift. Since an arbitrary logic value can be set to an arbitrary scan flip-flop by the scan shift, the problem of the controllability over the pseudo primary input lines is solved. Observation of the test response from the combinational circuit portion includes observation made directly by the primary outputs and observation made by means of the scan shift. Since an output value from an arbitrary scan flip-flop can be observed by the scan shift, the problem of the observability over the pseudo primary output lines is solved. In this way, according to the scan testing, it suffices to obtain test vectors and an expected test response using an automatic test pattern generation (ATPG) program.
Despite usefulness of the scan testing, the problem remains that power dissipation is quite high during a test as compared with ordinary operation. If a semiconductor logic circuit is constituted by a CMOS circuit, the power dissipation includes static power dissipation due to leakage current and dynamic power dissipation due to switching activity of logic gates and flip-flops. Moreover, the latter dynamic power dissipation includes shift power dissipation during shift activity and capture power dissipation during capture activity.
Generally, the number of clock pulses applied during the scan shift is large for one test vector. For example, to set new values to all the scan flip-flops in a certain scan chain, it is necessary to apply clock pulses up to those as many as the scan flip-flops. Due to this, the shift power dissipation increases, often resulting in excessive heat. The excessive heat may possibly damage the semiconductor logic circuit. Studies have been actively conducted for methods of reducing the shift power dissipation.
Meanwhile, the number of clock pulses necessary during the scan capture for one test vector is usually one per scan chain. Due to this, the problem of the heat due to the scan capture power dissipation does not occur. However, if the test response from the combinational circuit portion appearing on one pseudo primary output line is loaded into the scan flip-flops and the test response value differs from a value currently present in the scan flip-flop, an output value from the corresponding scan flip-flop changes. If the number of scan flip-flops having changed output values is large, power supply voltage temporarily drops due to switching activities of logic gates and the scan flip-flops. This phenomenon is also called “IR-(I: current and R: resistance) drop phenomenon”. The IR-drop phenomenon causes the circuit to malfunction, and a faulted test response value is often loaded into the scan flip-flops. A faulted test result that the semiconductor logic circuit that can operate normally at ordinary time is determined as a defective product in a test is thereby obtained. This results in yield loss. Particularly, if semiconductor logic circuits are increasingly made very large in scale, ultra-fine, and lower in power supply voltage, the yield loss caused by the faulted test result becomes conspicuous. It is, therefore, necessary to reduce capture power dissipation.
If a single clock signal is used during a test, scan capture power dissipation can be reduced using a clock gating scheme. However, the clock gating scheme greatly influences physical design of the semiconductor logic circuit. If multiple clock signals are used during a test, the scan capture power dissipation can be reduced using a one-hot scheme or a multiple-clock scheme. However, since the former scheme greatly increases test data volume and the latter scheme requires considerably high memory dissipation to generate test vectors, the both methods cast heavy burden on the ATPG. Therefore, to reduce the scan capture power dissipation, a scheme with less influence on the physical design, smaller increase in the test data volume, and slighter burden on the ATPG is desirable.
On the other hand, a test cube with don't-care bits logic values of which can be set to either 1 or 0 to achieve a predetermined object such as fault detection frequently appears in the process of generating test vectors according to the ATPG program. By contrast, a test input without don't-care bits including only a logic bit (bit having a logic value 0 or 1) is referred to as the “test vector” as already described. Furthermore, if a set of test vectors without don't-care bits is given, a part of bits of a part of the test vectors can be replaced by don't-care bits without changing the fault coverage of the test vector set. Namely, a test cube can be also obtained by a don't-care bits identification program. A cause for the presence of the test cube is as follows. To detect one or a plurality of target faults in the combinational circuit portion of the full-scan sequential circuit, it suffices to set necessary logic values to a part of bits on the primary input lines and the pseudo primary input lines. Since there is no influence on the detection of the target fault or faults whether 0 or 1 is set to each of the remaining bits, those remaining bits are regarded as don't-care bits for the target fault or faults.
Non-Patent Documents 1 to 3 relate to techniques for replacing a part of bits of a part of a set of test vectors without don't-care bits by don't-care bits without changing the fault coverage of the test vector set.
Non-Patent Document 1 uses a scheme called “Bit-Striping” for checking whether bits can operate as don't-care bits one bit by one bit so as to identify don't-care bits of each test vector. This scheme completely ignores the correlation among the test vectors. This scheme also has a problem that processing time increases in proportion to the number of bits.
According to Non-Patent Document 2, don't-care bits are identified based on a scheme called “XID”. Differently from the technique of Non-Patent Document 1, not each test vector but all the test vectors in a given test vector set are simultaneously processed by the XID scheme. Specifically, a fault that can be detected only in each test vector (referred to as “essential fault”) is obtained. Next, a logic value setting necessary to detect all essential faults is made by applying implication operation and logic justification of the ATPG. As a result, the other logic bits are replaced by don't-care bits. With this scheme, a simulation is not carried out on all input bits. Due to this, the scheme of Non-Patent Document 2 is more efficient and shorter in test application time than that proposed by Non-Patent Document 1. Nonetheless, no restrictive conditions are set for this don't-care-bit scheme. Namely, with this scheme, every logic bit may possibly be replaced by a don't-care bit.
According to Non-Patent Document 3, similarly to the above-stated Non-Patent Document 2, not each test vector but all the test vectors in a given test vector set are simultaneously processed. The difference of the technique of Non-Patent Document 3 from that of Non-Patent Document 2 is that it is not allowed to replace any of the logic bits by don't-care bits and that don't-care bits are identified only from a part of logic bits (referred to as “candidate bits”). Don't-care bits are not identified from logic bits other than the candidate bits (referred to as “fixed bits”). According to Non-Patent Document 3, don't-care bits are identified under restrictive conditions including candidate bits and fixed bits. The scheme of Non-Patent Document 3 is short in test application time similarly to Non-Patent Document 2. In addition, with the scheme of Non-Patent Document 3, don't-care bits can be identified efficiently for achieving a predetermined object. Obviously, since such object achievement efficiency depends on positions of don't-care bits, it is important to set the restrictive conditions including candidate bits and fixed bits according to the object.
A test cube with don't-care bits is only an intermediate appearing in the process of generating test vectors without don't-care bits. Due to this, it is necessary to assign a logic value 0 or 1 into each don't-care bit in the test cube. At the time of assignment, it is normal to decide a logic value (0 or 1) necessary to achieve a certain object for each don't-care bit. Non-Patent Document 4 relates to a technique for deciding a logic value for each don't-care bit in a test cube with a view of reducing scan capture power dissipation.
According to Non-Patent Document 4, three-valued (logic values 0, 1, and X representing don't-care) simulation is done to a test cube with don't-care bits obtained by various schemes in a combinational circuit portion of a full-scan sequential circuit, and test responses to the test cube are first obtained. Next, bit-pairs each including a pseudo input line bit and a pseudo output line bit are classified into Type-A bit-pairs each with only the pseudo input line bit being a don't-care bit, Type-B bit-pairs each with the pseudo output line bit being a don't-care bit, and Type-C bit-pairs with both the pseudo input line bit and the pseudo output line bit being don't-care bits. These bit-pairs are processed in order one pair by one pair. If a Type-A bit-pair is to be processed, a logic value of the corresponding pseudo output line bit is assigned to the pseudo input line bit that is the don't-care bit. If a Type-B bit-pair is to be processed, justification is performed so that a logic value of the pseudo input line bit appears on the pseudo output line bit that is the don't-care bit, thereby deciding a logic value of each of the don't-care bits in the test cube. If a Type-C bit-pair is to be processed, a logic value is assigned to the pseudo input line and justification is performed on the pseudo output line so that the same logic value (0 or 1) appears on each of the don't-care bits that are both the pseudo input line bit and the pseudo output line bit, respectively, thereby deciding a logic value of each of the don't-care bits in the test cube. Obviously, the assignment technique of Non-Patent Document 4 is characterized in that consideration is given only to one bit-pair including one pseudo input line bit and one pseudo output line bit when deciding the logic value of each of the don't-care bits in the test cube. The logic values thus decided are not necessarily overall optimum value.
[Non-Patent Document 1] R. Sankaralingam and N. A. Touba, “Controlling Peak Power During Scan Testing,” Proceedings of IEEE VLSI Test Symposium, pp. 153-159, 2002.
[Non-Patent Document 2] K. Miyase and S. Kajihara, “XID: Don't Care Identification of Test Patterns for Combinational Circuits,” IEEE Transactions on Computer-Aided Design, Vol. 23, pp. 321-326, 2004.
[Non-Patent Document 3] K. Miyase, S. Kajihara, I. Pomeranz, and S. Reddy, “Don't Care Identification on Specific Bits of Test Patterns,” Proceedings of IEEE/ACM International Conference on Computer Design, pp. 194-199, 2002.
[Non-Patent Document 4] X. Wen, H. Yamashita, S. Kajihara, L.-T. Wang, K. Saluja, and K. Kinoshita, “On Low-Capture-Power Test Generation for Scan Testing,” Proceedings of IEEE VLSI Test Symposium, pp. 265-270, 2005.